The present invention relates to an arrangement and method for repairing an integrated circuit.
German Patent Application No. 196 51 075.9-53 describes processors having a plurality of 2-dimensional or multidimensional arithmetic and logic units/cells. The computing power of such processors increases with the number of arithmetic and logic units present. Therefore, an attempt is made to integrate as many arithmetic and logic units as possible on one chip, which increases the area required. With an increase in area, there is also a higher probability of a chip having a manufacturing defect making it useless. All arithmetic and logic units arranged in matrix form have this problem, e.g., including other known types such as DPGAs, Kress arrays, systolic processors and RAW machines; likewise, some digital signal processors (DSPs) having more than one arithmetic and logic unit.
At the same time, all the aforementioned types require a great deal of testing, i.e., to detect faults, an especially large number of test cases must be generated and tested with respect to the functioning of the cells and the networking. Conventional methods such as BIST, boundary scan, etc. are difficult to integrate because of the large number of test vectors and they are also too time consuming and take up too much space.
Standard processors such as the x86 series, MIPS or ALPHA have a plurality of arithmetic and logic units which are driven at the same time by a VLIW command or with a time offset. In the future, the number of integrated units (integer units) and floating point units will continue to increase. Each unit must be tested adequately and must be largely free of defects.
Due to the increasing probability of defects with large chips, either only a very small number of cells can be integrated or production costs will increase greatly due to the resulting rejects. Very large chips will reach a maximum area beyond which a functional chip can no longer be produced. Due to the time consumed in testing according to conventional methods, there is a great increase in testing costs. Integrated BIST functions (built-in self-test) take up a great deal of area due to the high extra complexity, driving costs even higher and reducing manufacturing feasibility. In addition, this greatly increases the probability of a defect lying not within the actual function units but instead within the test structures.
Due to the increasing number of arithmetic and logic units, there is also an increase in the probability of defects. This means more rejects, causing manufacturing costs to increase. With an increase in area and a related increase in the number of transistors used, there is also an increase in probability of failure during use.
With regard to testing complexity and implementation of BIST, the discussion above regarding xe2x80x9cmultidimensional arrays of arithmetic and logic unitsxe2x80x9d also applies here.
The present invention provides for replacing defective cells with functional cells and reducing rejects. A cell can be replaced either by the test systems at the time of manufacture of the chips or even by the user in the completely assembled system. Test vectors can be generated according to the BIST principle within the chip, or outside the unit according to a new method to save on space and costs. In addition, a possibility of chips automatically repairing defects without requiring any additional external tool is described. All the tests and repairs can be performed during operation of the chips.
An additional PAE not used in normal operation (referred to below as PAER) is assigned to a group of cells which are referred to below as PAEs according to German Patent 196 51 075.9-53. The cells may be arithmetic and logic units of any type, configurable (programmable) logic cells or other cores having any desired function. Grouping of the PAEs in rows or columns is preferred in the grouping of PAEs and allocation of the PAER, because this simplifies the networking. With respect to future chip technologies, reference is made to a possible grouping of the PAEs within a 3rd dimension. Multiplexers are connected upstream from the inputs of the PAEs in such a way that the input of the first PAE in the row/column can also be switched to the input of the second PAE in the row/column, and then the input of the second PAE can be switched to the input of the third PAE and so forth. The input of the last PAE is switched to the input of the PAER. This means that if there is a defect in the first PAE, its function is replaced by the second PAE, the function of the second is replaced by the third and so forth, until the function of the last PAE is replaced by the PAER. If a PAE within the column/row is defective, the PAEs upstream from it are switched normally and after the position of the defective PAE, all functions are shifted by one PAE. For example, if PAE 4 is defective, then PAEs 1 . . . 3 execute their respective functions, while the input multiplexer of PAE 5 is switched so that it receives the data of PAE 4, the input multiplexer of PAE 6 receives the data of PAE 5 and so forth until the input of the PAER receives the data of the last PAE.
To supply the results back to the network in the proper sequence, multiplexers are also provided at the outputs of the PAEs, with the output multiplexer of PAE 1 either switching PAE 1 to the bus (if it is not defective) or if there is a defect, switching the output of PAE 2 to the bus, PAE 3 is switched to the bus instead of PAE 2, until the last PAE, where the PAER is switched in its place. If the defective PAE is in the middle of the row/column, the outputs are shifted exactly as already described above for the inputs.
Especially with a configurable logic and configurable arithmetic and logic units, there are additional bus systems to transfer the configuration data and control the configuration. These bus systems are also connected by multiplexers in the same way as the buses mentioned in this section. The same thing is also true of bus systems over which commands are written to the respective arithmetic and logic units with a matrix arrangement of arithmetic and logic units (e.g., systolic processors, SIMD, etc.). Basically any bus or any signal can be sent over multiplexers. Depending on the fault tolerance requirements, the clock signal, for example, can be sent over multiplexers to prevent a possible short circuit, or the clock signal may be sent directly to the cell because such a failure need not be compensated. The fault tolerance step can be defined in the structural details according to the requirements for each signal or each bus individually.
The concept of correcting faults within gate structures may also be applied to bus systems in which an additional bus (BUS R) is assigned to a number of buses (BUS 1 . . . BUS n). If one of the buses is defective (BUS d), its function is assumed by one of its neighboring buses (BUS (d+1)). The function of the neighboring bus (BUS (d+1)) is assumed by its neighboring bus (BUS (d+2)), etc., with the direction of the bus assuming the function always remaining the same until the function of BUS n is assumed by BUS R.
When multiplexer structures are used with bus systems, the usual multiplexers, decoders and gates, tristate gates or bidirectional multiplexers are used according to the prevailing connection structure and the direction of the data.
Two groups of successive multiplexers should always assume the same state, i.e., MUX 1=MUX 2=MUX 3=. . . =MUX n=state A, and MUX (n+1)=MUX (n+2)=MUX (n+3) . . . =MUX m=state B.
If no PAE is defective, then MUX 1=MUX 2=. . . MUX m=state A.
If the first PAE is defective, then MUX 1=MUX 2=. . . =MUX m=state B.
For example, if PAE 3 is defective, then MUX 1=MUX 2=state A, MUX 3=MUX 4=. . . =MUX m=state B, with PAER being assigned to PAE m in this example, i.e., PAER is directly next to PAE m.
The multiplexers are therefore controlled as follows, for example:
If PAER is assigned to PAE 1, the m . . . 1 sequence is inverted (defective PAE 1 corresponds to 0000 . . . 001, or defective PAE m corresponds to 1111 . . . 111).
Therefore, it is sufficient to store the number of the defective PAE and send it to a decoder which controls the states of the multiplexers on the basis of the table given above.
Any desired test strategies may be applied to this method, but it is advantageous to apply the methods according to the present invention.
The array of PAEs is loaded with one or more test algorithms which calculate one or more test vectors. At one edge of the array, the PAEs are wired as comparators so that the values calculated on the basis of the test vectors are compared to the setpoint results.
If the calculated result does not correspond to the setpoint results, there is a defect. The test data, i.e., the test algorithms, the test vectors and the setpoint results are present in an internal or external memory or are loaded by a higher level unit. In this test strategy, it is necessary for each test algorithm to be calculated at least twice, with the PAEs designed as comparators being on another edge (preferably the opposite edge) the second time to guarantee execution of the test algorithm on all PAEs. It is also conceivable for the comparators to be arranged in the interior of the PAE array, and with one test algorithm A and B each calculating one result A and B from left and right (top and bottom), where the results are sent to the comparators and must match. Depending on the type of test algorithm, the defective PAE may be tracked back on the basis of the defect or not. If the algorithm supports tracking of the defect, the corresponding multiplexer states of the row/column in which the defective PAE is located are changed and sent to the multiplexers. The test algorithm in which the test is failed is executed again to check on freedom from defects, which should now prevail. If the unit is still defective, a check must be performed to determine whether an additional or other PAEs are defective. Execution of the test algorithm and generation of the multiplexer states adapted to the defect are iterative processes. It is not usually sufficient to implement just one test algorithm, but instead multiple different test algorithms may be implemented, each being checked with multiple test vectors. Only in this way can a maximum fault detection rate be achieved.
At the same time, the bus crosslinking must be changed from one test algorithm to the next, so that the bus systems are also checked adequately.
The various embodiments of the test algorithms will not be discussed in further detail here because this is not entirely relevant for the basic method according to the present invention.
Units such as described in German Patent Application No. 196 51 075.9-53, DPGAs, Kress arrays, systolic processors and RAW machines all have in common an integrated memory which is assigned to one or more PAEs and determines the function of the arithmetic and logic unit(s).
According to the basic BIST principle, the memory is expanded by a region (TestMEM) containing the test algorithms and vectors. This memory can be fixed in the form of a ROM or it may be rewritable by (E)EPROM, flash ROM, NV-RAM or the like.
To perform a self-test, the system jumps to a memory location within the TestMEM and executes the test routine stored there (internal driven self-test=IDST). Except for the expansion of the memory (by the TestMEM) and an analyzer unit for the comparators described above (ErrorCHK), no other additional units typical of BIST are needed on the chip.
The reduction in components on a memory expansion (TestMEM) and an analyzer unit of the comparators (ErrorCHK) permit an additional, even less expensive and space-saving variant. No internal TestMEM is implemented here, but instead the usual internal memory is loaded from the outside with the test algorithm and the test vectors (external driven self-test=EDST); this means that the BIST test data is shifted outward and regarded as a normal program. Then the test algorithm is executed. As an alternative, the test algorithm may also be loaded successively from an external memory during the execution and decoded. Only the ErrorCHK unit must still be integrated on the chip. There are several possibilities for loading the test algorithm and the test vectors from the outside into the chip-internal memory (memories). In principle, the process can take place through a functionally higher level CPU or computer unit (HOST), with the latter loading the test data (test algorithm and test vectors) onto the chip (download) or the chip loading the test data automatically from an external (dual-ported) RAM or read-only memory such as ROM, (E)EPROM, flash ROM, NV-ROM or the like.
Conventional BIST methods usually perform the self-test only during the chip RESET phase, i.e., shortly after applying a voltage (when turned on). In contrast, it is possible or practical to perform the methods described here on the chips while the programs are running. For example, a complete test of the chip can be performed during the RESET phase and part of the available test data can be loaded during execution of the application program or during IDLE cycles, i.e., periods of time when no program is running on the chips or the chip is in a waiting mode. This is readily possible by the fact that one of the test algorithms is activated in the internal memory during IDLE cycles or is loaded into the unit from an external memory or host. It is of course possible to select one or more of the plurality of available test algorithms and test data in part, in which the number of selected test data can be defined on the basis of the length of the IDLE cycle. New test data can be loaded until the IDLE cycle is ended by the arrival of new data to be processed, by a new program to be executed or by another request.
Another possibility is the fixed integration of test strategies into the application programs to perform tests during processing of the application program. In both cases, the relevant data in the array is saved before calling up the test algorithms. One option is to save the data either in internal memory areas (cf. PACT04) or in memories connected externally. After executing the test algorithms, the data is read back before the normal program processing.
One alternative for increasing the execution speed is to implement in addition to each register (Reg-n, n xcex5 N) an additional register (TestReg-n, n xcex5 N) which is used only for the test algorithms. Before execution of the test algorithms, the TestReg-n are connected by multiplexers/demultiplexers (gates) and used for the test. The Reg-n remain unchanged. After execution of the test algorithms, the Reg-n are connected again.
If the test strategy provides for testing of only those cells whose data is no longer relevant subsequently, the data need not be saved and loaded.
If a PAE (or a bus) is recognized as defective, its number, i.e., the state vector (defect identifier) of the assigned multiplexer must be stored first to control the multiplexers and also to be available immediately for a chip RESET. Therefore, the defect identifier may be stored
1. internally in the chip in a programmable read-only memory ((E)EPROM, flash ROM, NV-RAM, etc.),
2. externally in a programmable read-only memory ((E)EPROM, flash ROM, NV-RAM, etc.), or
3. externally in the HOST within the program to be executed, in its programmable read-only memory ((E)EPROM, flash ROM, NV-RAM, etc.) or in other storage media (magnetic, optical, etc.).
Usually after detection of a defect, the defective cell is tracked on the basis of the defective performance detected. This is possible with appropriate test algorithms if there is an additional algorithm for tracking the defect. If the test is controlled by a HOST, the tracking can be performed on the HOST. However, if there is no HOST, tracking often cannot be integrated into the defective chip or is too complicated. It is possible that a loadable counter be integrated upstream from each decoder. In the normal case, the number of the defective PAE is loaded into the counter, after which the decoder controls the states of the multiplexers as described above. If it is not known which PAE is defective, beginning at PAE 0 or PAE m the counter can function in response to any potentially defective PAE by reducing the count by one PAE (counting from PAE m) or increasing the count by one (counting from PAE 0) after each unsuccessful test until the defective PAE is reached and the test takes place normally. The count then reached is stored as the state vector for controlling the multiplexers and represents the defective PAE. If a functional count is not found, there is either another defect (possibly in another row/column or a bus error) or more than a PAE is defective. One disadvantage when using counters is that all possibilities are permutated until the defective PAE has been located.
Another possibility, although it requires a greater implementation expense, is to use look-up tables which select the corresponding defective PAE on the basis of the test algorithm just executed and the resulting error state in ErrorCHK. The test algorithms and look-up tables being coordinated. The coordination will not be discussed further here because it is highly chip-specific and does not depend on the basic principle.
Processors includes a plurality of integer units and floating point units. Therefore, the method described here can be applied directly to these units by having an additional unit in each case which will be available for possible defects. The test of the processors can be performed at the manufacturer""s, during startup of the computer or also during the operating time. A test maybe performed during boot-up, i.e., starting up of the computer after a reset, which is performed with PCs of the BIOS type (BIOS=basic input output system). The corresponding state vectors of the multiplexers can be stored either on the processor or in an external memory, e.g., the battery-buffered real-time clock (RTC) in a PC.
The present invention provides for replacing defective units, which are designed as arithmetic and logic units, for example, but in general may be any desired unit of a chip, with a functional unit. The present invention provides a method with which self-tests can be performed more easily, less expensively and before or during the running of the application program. The present invention greatly increases fault tolerance during operation, which is advantageous for failure-critical applications such as power plant operations, aviation and space travel or in the military, for example.